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        <description>The Micro Architecture at Santa Cruz (MASC) group was founded on 2004. Its main focus is computer architecture research. https://masc.soe.ucsc.edu/</description>
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            <title><![CDATA[Live Hardware Demo with ESESC]]></title>
            <link>https://diode.zone/w/jtvtM5L1TnAaujQzi5TAFB</link>
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            <pubDate>Fri, 08 May 2020 01:18:26 GMT</pubDate>
            <description><![CDATA[This demo from 2014 shows the goals for the MASC group hardware development flow. It includes an interactive demo with ESESC based on "LiveSim: Going Live with Microarchitecture Simulation" from HPCA 2015. The demo includes the javascript GUI tha...]]></description>
            <content:encoded><![CDATA[<p>This demo from 2014 shows the goals for the MASC group hardware development flow. It includes an interactive demo with ESESC based on "LiveSim: Going Live with Microarchitecture Simulation" from HPCA 2015.</p>
<p>The demo includes the javascript GUI that was used at the time (no longer mantained) LiveOS project (<a href="https://github.com/masc-ucsc/liveos" target="_blank" rel="noopener noreferrer">https://github.com/masc-ucsc/liveos</a>)</p>
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            <media:title type="plain">Live Hardware Demo with ESESC</media:title>
            <media:description type="plain">This demo from 2014 shows the goals for the MASC group hardware development flow. It includes an interactive demo with ESESC based on "LiveSim: Going Live with Microarchitecture Simulation" from HPCA 2015. The demo includes the javascript GUI tha...</media:description>
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            <title><![CDATA[Live Hardware Development and Hardware Description Language Integration]]></title>
            <link>https://diode.zone/w/5WA39sRtMKwpx9pewPafue</link>
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            <pubDate>Fri, 08 May 2020 01:04:56 GMT</pubDate>
            <description><![CDATA[The hardware development cycle is prolonged and tedious compared to the faster design turnaround time of the software development model. In Microarchitecture Santa Cruz group, we have built a ""live"" hardware development flow called LiveHD. The u...]]></description>
            <content:encoded><![CDATA[<p>The hardware development cycle is prolonged and tedious compared to the faster design turnaround time of the software development model. In Microarchitecture Santa Cruz group, we have built a ""live"" hardware development flow called LiveHD. The ultimate goal of LiveHD is to provide design feedback in a few seconds with the designer's preferred hardware description languages (HDLs). Prior work of LiveHD uses the LGraph as the intermediate representation (IR) to express the netlist. In the advancement thesis, we first present the new LGraph IR enhancements. Our new memory map library is now used in LGraph to enables fast load/unload LGraph from/to the disk. LGraph also adds the support of hierarchical traversal and attribute features, which allows the integrated tools to execute their algorithm engine hierarchically.</p>
<p>Two bottlenecks in the LiveHD framework still potentially hinder our goal in achieving live feedback with HDLs. First, LiveHD only interfaces one HDL, System Verilog, by using Yosys. Second, LiveHD uses LGraph as the internal low-level IR, but the semantic gap between high-level modern HDLs and the LGraph IR makes it hard to interface directly. We further propose a language-neutral abstract syntax tree (LNAST) to address these problems. LNAST is a tree-based IR that bridges modern HDLs into LiveHD; it is a higher-level representation of a design than LGraph. LGraph and LNAST  representations will be seamlessly converted to each other. As a high-level IR, LNAST can capture high-level semantics from different HDLs in the common tree structure. This enables HDLs to leverage the live synthesis and simulation framework in LiveHD. Another key motivation for designing LNAST is the generation of human-readable C++ and HDLs, which will be essential infrastructure for our future research projects of hardware simulation and Pyrope compiler verification.</p>
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